8 Bit Adder CMOS Design

Overview of the project

As part of the course project on VLSI Design, me and my team mates designed an 8-bit Adder using cadence. I was in charge of the Silicon Layout Design.

I was able to design a compact layout occupying the smallest area in the class.

Layout of the 8-Bit Ripple Carry Adder

layout of the 8-Bit Carry Bypass Adder

Layout of the 8-Bit NAND Gate

Layout of the Full Adder with XOR Output

Layout of 2-1 Mux

Layout of Inverter

Layout of NAND Gate